Hardware protection against bit-flips during I/O between storage and DRAM?
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If a motherboard supports ECC DRAM, then it has a 72 bit bus between the DRAM slot and the memory controller. 64 data bits + 8 parity bits for SECDED. Nowadays, most CPUs have the memory controller integrated inside. So, the moving bits between the DIMM and the CPU are protected against one single bit error per 8 bits.
Is there also any kind of correction/detection of bit-flips during the process of reading/writing between non-volatile memory and volatile memory possible?
Often storage devices are connected to a PCH, which is connected to the CPU. Sometimes storage devices are connected to the CPU directly.
Anyway, is there somehow any hardware protection against data corruption during I/O between storage and DRAM?
storage ecc data-integrity dram dma
asked Nov 21 at 16:51
FPU
265
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up vote
0
down vote
favorite
If a motherboard supports ECC DRAM, then it has a 72 bit bus between the DRAM slot and the memory controller. 64 data bits + 8 parity bits for SECDED. Nowadays, most CPUs have the memory controller integrated inside. So, the moving bits between the DIMM and the CPU are protected against one single bit error per 8 bits.
Is there also any kind of correction/detection of bit-flips during the process of reading/writing between non-volatile memory and volatile memory possible?
Often storage devices are connected to a PCH, which is connected to the CPU. Sometimes storage devices are connected to the CPU directly.
Anyway, is there somehow any hardware protection against data corruption during I/O between storage and DRAM?
storage ecc data-integrity dram dma
asked Nov 21 at 16:51
FPU
265
add a comment |
up vote
0
down vote
favorite
up vote
0
down vote
favorite
If a motherboard supports ECC DRAM, then it has a 72 bit bus between the DRAM slot and the memory controller. 64 data bits + 8 parity bits for SECDED. Nowadays, most CPUs have the memory controller integrated inside. So, the moving bits between the DIMM and the CPU are protected against one single bit error per 8 bits.
Is there also any kind of correction/detection of bit-flips during the process of reading/writing between non-volatile memory and volatile memory possible?
Often storage devices are connected to a PCH, which is connected to the CPU. Sometimes storage devices are connected to the CPU directly.
Anyway, is there somehow any hardware protection against data corruption during I/O between storage and DRAM?
storage ecc data-integrity dram dma
asked Nov 21 at 16:51
FPU
265
If a motherboard supports ECC DRAM, then it has a 72 bit bus between the DRAM slot and the memory controller. 64 data bits + 8 parity bits for SECDED. Nowadays, most CPUs have the memory controller integrated inside. So, the moving bits between the DIMM and the CPU are protected against one single bit error per 8 bits.
Is there also any kind of correction/detection of bit-flips during the process of reading/writing between non-volatile memory and volatile memory possible?
Often storage devices are connected to a PCH, which is connected to the CPU. Sometimes storage devices are connected to the CPU directly.
Anyway, is there somehow any hardware protection against data corruption during I/O between storage and DRAM?
storage ecc data-integrity dram dma
storage ecc data-integrity dram dma
asked Nov 21 at 16:51
FPU
265
asked Nov 21 at 16:51
FPU
265
edited Nov 22 at 11:40
asked Nov 21 at 16:51
FPU
265
asked Nov 21 at 16:51
FPU
265
asked Nov 21 at 16:51
FPU
265
265
add a comment |
add a comment |
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